/*
 * VS1053B_Config.h
 *
 *  Created on: 2021年4月12日
 *      Author: slh95
 */

#ifndef VS1053B_VS1053B_CONFIG_H_
#define VS1053B_VS1053B_CONFIG_H_

#include "stm32f1xx_hal.h"

#define SET_REG_BITS(reg_val, bits) (reg_val |= (1<<bits))
#define RESET_REG_BITS(reg_val, bits)   (reg_val &= (~(1<<bits)))

#define VS1053B_WRITE_CMD       (0x02)
#define VS1053B_READ_CMD        (0x03)

#define VS1053B_MODE_REG		(0x00)		// Mode control, Reset value 0x4800
#define VS1053B_STATUS_REG		(0x01)		// Status of VS1053B, Reset value 0x000C
#define VS1053B_BASS_REG		(0x02)		// Built-in base/treble control
#define VS1053B_CLOCKF_REG		(0x03)		// Clock freq+multiplier
#define VS1053B_DECODE_T_REG	(0x04)		// Decode time in seconds
#define VS1053B_AUDATA_REG		(0x05)		// Misc.audio data
#define VS1053B_WRAM_REG		(0x06)		// RAM write or read
#define VS1053B_WRAMADDR_REG	(0x07)		// Base addr for RAM RW
#define VS1053B_HDAT0_REG		(0x08)		// Stream header data0, read only
#define VS1053B_HDAT1_REG		(0x09)		// Stream header data1, read onl
#define VS1053B_AIADDR_REG		(0x0A)		// Start addr of app
#define VS1053B_VOL_REG			(0x0B)		// Volume control
#define VS1053B_AICTRL0_REG		(0x0C)		// Application control reg 0
#define VS1053B_AICTRL1_REG		(0x0D)		// Application control reg 0
#define VS1053B_AICTRL2_REG		(0x0E)		// Application control reg 0
#define VS1053B_AICTRL3_REG		(0x0F)		// Application control reg 0

typedef enum
{
    SM_DIff = 0,        // Differential, 0-normal in-phase aduio; 1-left channel inverted
    SM_LAYER12,        // Allow MPEG layers Ⅰ & Ⅱ, 0-No; 1-Yes
    SM_RESET,        // Soft reset, 0-noreset; 1-reset
    SM_CANCLE,        // Cancle decoding current file, 0-No; 1-Yes
    SM_EARSPEAKER_LO,        // EarSpeaker low setting , 0-off; 1-acctive
    SM_TESTS,        // Allow SDI Tests, 0-Not allowed; 1-allowed
    SM_STREAM,        // Stream mode, 0-No; 1-Yes
    SM_EARSPEAKER_HI,        // EarSpeaker high setting , 0-off; 1-acctive
    SM_DACT,        // DCLK active edge, 0-rising; 1-falling
    SM_SDIORD,        // SDI bit order, 0-MSB First; 1-LSB First
    SM_SDISHARE,        // Share SPI CS, 0-No; 1-Yes
    SM_SDINEW,        // VS1002 native SPI modes, 0-No; 1-Yes
    SM_ADPCM,        // ADPCM recording active, 0-No; 1-Yes
    SM_RESERVES,    // Reserved
    SM_LINE1,        // mic/line1 selector, 0-MICP; 1-LINE1
    SM_CLK_RANGE,    // Input clock range, 0-12~13MHz; 1-24~26MHz
}VS1053B_MODE;

typedef enum
{
    SS_DO_NOT_JUMP = 15,        // Header in decode, do not fast forward/rewind
    SS_SWING = 12,        // Set swing to +0 dB, +0.5 dB, .., or +3.5 dB
    SS_VCM_OVERLOAD = 11,        // GBUF overload indicator ’1’ = overload
    SS_VCM_DISABLE = 10,        // GBUF overload detection ’1’ = disable
    SS_VER = 4,        // Version
    SS_APDOWN2 = 3,        // Analog driver powerdown
    SS_APDOWN1 = 2,        // Analog internal powerdown
    SS_AD_CLOCK = 1,        // AD clock select, ’0’ = 6 MHz, ’1’ = 3MHz
    SS_REFERENCE_SEL = 0,        // Reference voltage selection, ’0’ = 1.2V, ’1’ = 1.65V
}SCI_STATUS;

typedef enum
{
	ST_AMPLITUDE = 12,		// Treble Control in 1.5 dB steps (-8..7, 0 = off)
	ST_FREQLIMIT = 8,		// Lower limit frequency in 1000 Hz steps (1..15)
	SB_AMPLITUDE = 4,		// Bass Enhancement in 1 dB steps (0..15, 0 = off)
	SB_FREQLIMIT = 0,		// Lower limit frequency in 10 Hz steps (2..15)
}SCI_BASS;

typedef enum
{
	SC_MULT = 13,		// Clock multiplier
	SC_ADD = 11,		// Allowed multiplier addition
	SC_FREQ = 0,		// Clock frequency
}SCI_CLOCKF;

#endif /* VS1053B_VS1053B_CONFIG_H_ */
